A PC video display monitor may have several resolutions because of various program requirements. An external synchronization signal is typically used to synchronize these resolutions. Each resolution typically has its own frequency, and the external synchronization signal pulse width may vary depending on its frequency. The frequency range is typically from 30 kHz to 95 kHz.
Power supplies in these display monitors typically use a technique called switched-mode pulse width modulation ("PWM"). Switched-mode PWM synchronizes the switching frequency of the power supply to the display monitor horizontal frequency in order to prevent picture interrupt and to address electromagnetic compatibility/electromagnetic interference (EMC/EMI) issues. Because the horizontal frequency is at least 30 kHz, the switching frequency of the power supply must be set to a frequency somewhat lower than 30 kHz.
With such a variety of frequencies and resolutions, it is difficult for one designing a power supply to use the external synchronization signal to synchronize the PWM controller power supply to the display monitor. One method of synchronizing these devices is to use the turns ratio method to extract from the yoke extra flyback voltage to generate a synchronous signal having an amplitude of about 30V. However, this signal requires a resistor/capacitor network to reduce the voltage level and improve its shape.
Another synchronization method requires a synchronization signal having a clock width of approximately 1 .mu.s or more and an amplitude exceeding a certain voltage. Such a method is used by SGS-Thomson Microelectronics in its L4981A Power Factor Corrector ("PFC") integrated circuit. The L4981A requires the external synchronization pulse width to be greater than 800 ns and the signal voltage to be greater than 3.5V. In that scenario, as shown in the timing diagram in FIG. 1, a ramp waveform used by the circuit to generate an output clock signal must be kept low until the external synchronization pulse ends, reducing the duty cycle of the output clock. FIG. 1(a) shows the external synchronization signal, SYNC. FIG. 1(b) shows a ramp voltage waveform V.sub.T which has a slope controlled by an RC time constant. FIG. 1(c) shows the output that is used in the PFC circuit. When SYNC is low ("asynchronous operation"), V.sub.T ramps up. When V.sub.T is greater than a preset low threshold voltage 118, the output is high. As soon as V.sub.T crosses a preset high threshold voltage 112, the output goes low, causing V.sub.T to ramp downward. When V.sub.T crosses low threshold voltage 118, the output goes high which reverses the ramp waveform and the cycle repeats. As shown in FIG. 1, the output has a duty cycle of approximately 87% between times t.sub.0 and t.sub.1.
When the SYNC signal begins cycling ("synchronous operation"), a high SYNC signal causes V.sub.T to ramp downward and the output to go low. However, unlike before when V.sub.T crossed low threshold voltage 118 and caused the output to go high, when SYNC is high, the output remains low. This prior art synchronization method requires the SYNC signal to be high for at least time interval 124, between times t.sub.2 and t.sub.4, and V.sub.T must be kept low during time interval 130, from time t.sub.3 to time t.sub.4, until the SYNC pulse ends. The L4981A requires that time interval 124 be at least 800 ns, and it is typically more. Because of this restriction, the duty cycle of the output may be reduced significantly, to, for example, approximately 60% between times t.sub.4 and t.sub.5.